Path: utzoo!utgpu!water!watmath!clyde!cbosgd!ihnp4!ptsfa!ames!pasteur!ucbvax!decvax!decwrl!sun!pitstop!sundc!seismo!uunet!iconsys!kolob!rorden From: rorden@kolob.UUCP (Randy Rorden) Newsgroups: comp.arch Subject: Re: Performance increase - a suggestion (really sequent cache) Message-ID: <179@kolob.UUCP> Date: 22 Jan 88 05:45:30 GMT References: <39245@sun.uucp> Lines: 42 in article <39245@sun.uucp>, petolino%joe@Sun.COM (Joe Petolino) says: > > [in response to request for references on cache ownership protocols] > > The earliest references I could find by digging through my old Alan Jay Smith > papers are: > > C.K. Tang, "Cache System Design in the Tightly Coupled Multiprocessor > System", Proc. NCC, 1976. > > Lucien Censier and Paul Feautrier, "A New Solution to Coherence Problems > in Multicache Systems", IEEETC, C-27, 12, Dec 1978. > > I have no idea whether either of these papers actually describes an ownership > protocol. > > -Joe I ran across the following article which describes how to use a Shared bit and Dirty bit for cache consistency management in a multiprocessor system: Charles P. Thacker and Lawrence C. Stewart, "Firefly: a Multiprocessor Workstation", Proc. ASPLOS II, 1987. On another aspect of the Sequent bus interface - I once read an article that explained that it uses a request/response type protocol to avoid tying up the bus for the entire length of a read or write access. It also mentioned that several processors could have requests pending at the same time but that somehow they avoided sending requests to devices that already had "full" request queues. This is the part I couldn't figure out - does each processor "count" how many requests and replies have been transacted with each possible device? Or do they just monitor how many total requests are pending and assume the worst case that they all went to the same device? Either of these methods requires some understanding of how deep a given device's request queue is. Randy Rorden {ihnp4,byuadam,uunet}!iconsys!rorden Icon International, Inc. ARPANET: icon%byuadam.bitnet@wiscvm.wisc.edu Orem, Utah 84058 BITNET: icon%byuadam.bitnet (801) 225-6888