Path: utzoo!mnetor!uunet!tektronix!sequent!mntgfx!mbutts From: mbutts@mntgfx.mentor.com (Mike Butts) Newsgroups: comp.arch Subject: Re: Performance increase - a suggestion Message-ID: <1988Jan18.114940.201@mntgfx.mentor.com> Date: 18 Jan 88 19:49:36 GMT References: <235@unicom.UUCP> <844@ima.ISC.COM> Organization: Mentor Graphics Corporation, Beaverton Oregon Lines: 37 Keywords: bandwidth datapath 128 Summary: Wider datapaths are very fine, but the pin count demands are a barrier. In article <844@ima.ISC.COM>, johnl@ima.ISC.COM (John R. Levine) writes: > In article <235@unicom.UUCP> physh@unicom.UUCP writes: > > It seems to me that one way to get a further increase in > >performance without increasing clock speeds and thus memory and other > >chip costs, would be to leave the processor at 32 bits and increase the > >external data path width to say 128 bits. Then it may be possible to > >get at least one instruction per fetch. ... > > This is a great idea, but one that has been well known for a long time. The > 360/85, just about the first commercial machine with a cache, did exactly that > for the path from core (and I mean core) to the cache. It still seems to be a > standard technique in machines that have separate buses for memory and I/O and > so avoid issues like what a 128 bit path to a serial terminal means. > This is indeed a fine idea, both for data and for instructions, but the big problem with wider datapaths nowadays is the pin count costs on the CPU chip. When fast computers were built at the board level, very wide busses were relatively easy to achieve. Now there's a great speed advantage from having the whole CPU on one chip, but VLSI packages have severe pin count limitations. More than 100-150 pins on a chip gets very expensive very fast, and more than 256 becomes untestable most places. This is at least one reason why MIPS and others must go to the trouble to double-clock their busses. Also, driving lots of outputs from high to low at once will put a big bounce on the chip's internal ground system, risking dropped bits or even destructive latchup. I think the tension between wide busses and packaging is one of the toughest problems faced by CPU engineers these days. -- Mike Butts, Research Engineer 503-626-1302 Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton OR 97005 ...!{sequent,tessi,apollo}!mntgfx!mbutts OR mbutts@pdx.MENTOR.COM These are my opinions, & not necessarily those of Mentor Graphics.