Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!umd5!purdue!i.cc.purdue.edu!j.cc.purdue.edu!pur-ee!uiucdcs!uxc.cso.uiuc.edu!ccvaxa!aglew
From: aglew@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: Performance increase - a suggestion
Message-ID: <28200088@ccvaxa>
Date: 18 Jan 88 13:40:00 GMT
References: <235@unicom.UUCP>
Lines: 35
Nf-ID: #R:unicom.UUCP:235:ccvaxa:28200088:000:1935
Nf-From: ccvaxa.UUCP!aglew    Jan 18 07:40:00 1988


>/* Written  2:43 pm  Jan 17, 1988 by tim@amdcad.AMD.COM in ccvaxa:comp.arch */
>In article <221@imagine.PAWL.RPI.EDU> userfe0e@mts.rpi.edu (George Kyriazis) writes:
>|   The only problem when doing that is jump instructions.  Assume that memory
>| operates at its fastest possible speed.  If you meet a jump instruction
>| in the middle of the 128-bit word, you'll have to (more or less) execute
>| all the rest up till the end of the fetch.  Some RISC CPU's have done this
>| but for only one instruction.  Can a compiler succesfully put 3 useful
>| instructions after the jump??  Maybe it sounds too cheap: "After any jump
>| the CPU executes at most three instructions after it". (Actually it turns
>| out that the jump has to be in the first of the 4 instructions in the 128-bit
>| word, so as the memory can get the right address.) 
>
>It is very hard to effectively schedule more than 1 instruction after a
>delayed-branch, and even more prohibitive to force branches to occur
>only at 4-instruction boundaries.  A solution to this problem is to
>throw away the instructions coming from memory, sourcing them instead
>from a cache while the instruction stream is restarted.  This is what
>the Branch-Target Cache is for on the Am29000.
>
>	-- Tim Olson

Another approach is to execute all of the instructions come what may.
This is the VLIW, trace-scheduling, approach commercialized by Multiflow.



Andy "Krazy" Glew. Gould CSD-Urbana.    1101 E. University, Urbana, IL 61801   
    aglew@gould.com     	- preferred, if you have nameserver
    aglew@gswd-vms.gould.com    - if you don't
    aglew@gswd-vms.arpa 	- if you use DoD hosttable
    aglew%mycroft@gswd-vms.arpa - domains are supposed to make things easier?
   
My opinions are my own, and are not the opinions of my employer, or any
other organisation. I indicate my company only so that the reader may
account for any possible bias I may have towards our products.