Path: utzoo!mnetor!uunet!husc6!bbn!rochester!PT.CS.CMU.EDU!K.GP.CS.CMU.EDU!lindsay
From: lindsay@K.GP.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: RISC criteria (was Intel 432)
Message-ID: <701@PT.CS.CMU.EDU>
Date: 23 Jan 88 02:22:54 GMT
References: <243@spar.SPAR.SLB.COM> <2707@omepd> <1071@cpocd2.UUCP> <7246@apple.UUCP>
Sender: netnews@PT.CS.CMU.EDU
Organization: Carnegie-Mellon University, CS/RI
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In article <1071@cpocd2.UUCP> howard@cpocd2.UUCP (Howard A. Landman) writes:
>If anyone sees a photo of the chip, here's an easy way to tell RISC from CISC:
>Identify the datapath and RAM (including register file and cache).  If they
>add up to less than half the chip area, it's a CISC.  That's because the rest
>is probably all control, and any chip that's more than half control does not
>have a simple architecture.

Some recent chips seem to put more real estate into bonding pads and pin
drivers, than into anything else. I assume that the power consumption is
there, too.
-- 
	Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science