Path: utzoo!utgpu!water!watmath!clyde!rutgers!ames!pasteur!ucbvax!ucsd!ucsdhub!hp-sdd!hplabs!hp-pcd!uoregon!omepd!mipos3!td2cad!cpocd2!howard
From: howard@cpocd2.UUCP (Howard A. Landman)
Newsgroups: comp.arch
Subject: Re: RISC criteria (was Intel 432)
Message-ID: <1095@cpocd2.UUCP>
Date: 28 Jan 88 22:10:14 GMT
References: <243@spar.SPAR.SLB.COM> <2707@omepd> <1071@cpocd2.UUCP> <7246@apple.UUCP> <701@PT.CS.CMU.EDU>
Reply-To: howard@cpocd2.UUCP (Howard A. Landman)
Organization: Intel Corp. ASIC Systems Organization, Chandler AZ
Lines: 25

In article <1071@cpocd2.UUCP> howard@cpocd2.UUCP (Howard A. Landman) writes:
>If anyone sees a photo of the chip, here's an easy way to tell RISC from CISC:
>Identify the datapath and RAM (including register file and cache).  If they
>add up to less than half the chip area, it's a CISC.  That's because the rest
>is probably all control, and any chip that's more than half control does not
>have a simple architecture.

In article <701@PT.CS.CMU.EDU> lindsay@K.GP.CS.CMU.EDU (Donald Lindsay) writes:
>Some recent chips seem to put more real estate into bonding pads and pin
>drivers, than into anything else. I assume that the power consumption is
>there, too.

As linewidths shrink, pads do not, so they do consume a lot of nanoacreage.
This was so obvious to me that I didn't even think to mention it.  To be
accurate, I should have said "the chip core area (excluding pads)", not
"the chip area".  Sorry if anyone got confused.

As I've pointed out in another posting, this was meant to be a quick rule of
thumb for guessing, not a definition of RISC or CISC.

-- 
	Howard A. Landman
	{oliveb,hplabs}!intelca!mipos3!cpocd2!howard
	howard%cpocd2.intel.com@RELAY.CS.NET
	"... all the words float in sequence.  No one knows what they mean, ..."