Path: utzoo!utgpu!water!watmath!clyde!cbosgd!ihnp4!ptsfa!lll-tis!mordor!sri-spam!rutgers!rochester!ritcv!cci632!ccicpg!harald
From: harald@ccicpg.UUCP ( Harald Milne)
Newsgroups: comp.sys.amiga
Subject: Re: Still More 68020 Questions
Message-ID: <9750@ccicpg.UUCP>
Date: 23 Jan 88 13:37:48 GMT
References: <8801081459.AA16543@decwrl.dec.com> <8822@ccicpg.UUCP> <4795@videovax.Tek.COM>
Organization: CCI CPD, Irvine CA
Lines: 53

In article <4795@videovax.Tek.COM>, stever@videovax.Tek.COM (Steven E. Rice, P.E.) writes:
> In article <8822@ccicpg.UUCP>, Harald Milne (harald@ccicpg.UUCP) replied
> to some questions from article <8801081459.AA16543@decwrl.dec.com>, by
> plouff@nac.dec.com (08-Jan-1988 0946). 
> > If memory is written to without the CPU's knowledge, then that 
> > "hit" in the cache is "dirty". For the 68020 this should not be a big deal.

	From giving thought to what Steve said below, I think the above needs
to be answered a little differently. I overlooked the possibility instructions
can be DMAed into CHIP RAM. It appears (That is assuming 68020 boards do run
with cache enabled in CHIP RAM) that Amiga's OS would have to purge the cache.

	Since I don't know what the Amiga's OS does internally, specific to
the 68020, somebody from CBM would have to answer this question.

	Then again, I could be making a wrong assumption here.

	Does anybody know?

> > 	Now if we were talking about the 68030, we would be getting into big
> > trouble, since the 68030 also caches data. The Amiga with all her
> > coprocessors writing into memory, could not garentee data is not "dirty"
> > without bus watching techniques (The same problem occurs in multi-processing
> > environments).
> > 
> > 	I guess that means the 68030 cache has gotta go! 8^(
> 
> Fortunately, no!  There is an input, Cache Inhibit In (CIIN*), which
> inhibits cacheing of data and/or instructions on a cycle-by-cycle basis.
> By asserting CIIN* on each access to CHIP RAM, you will prevent the
> cacheing of data (and instructions) that come from the area accessible
> to the blitter, et. al.
> 
> As long as you keep your instructions, stack, and non-displayed data in
> FAST RAM, you will still have the caches working for you.  8^)
> 
> 					Steve Rice

	Now the question is, is there a signal present that indicates
CHIP/FAST ram access? 

	Is it present on the A2000 MMU conector?

	Im not sure I can trust my outdated A2000 schematics in my A2000
manual, which I don't have with me at this present time.

	Sorry about all the questions.


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