Path: utzoo!utgpu!water!watmath!clyde!burl!codas!killer!bobc
From: bobc@killer.UUCP (Bob Calbridge)
Newsgroups: comp.sys.cbm
Subject: vdc
Keywords: vdc video display
Message-ID: <2951@killer.UUCP>
Date: 16 Jan 88 23:39:34 GMT
Distribution: na
Organization: The Unix(R) Connection, Dallas, Texas
Lines: 15

Those of you who have mentioned the upgrade to the vdc might be
able to answer a question concerning that chip.  There is a 
register that controls the starting address of the character set.
It is the upper three bits of register 28 that does the controlling.
The article in The Transactor did not specify just how this works.
If the available memory were only 16K long then I would assume that
it controlled the setting in steps of 2K.  But if the chip can 
address up to 64K then it could be steps of 8K.  Does anyone know which
of these it is?  Is there a better source on the VDC with a greater
explanation on the use of each register?  The article was informative 
but not quite enough.
Thanks in advance.

Best,
Bob