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From: bobmon@iuvax.UUCP (Bobmon)
Newsgroups: comp.misc,comp.sys.m68k,comp.sys.mac,comp.sys.ibm.pc
Subject: Re: The New Chips
Message-ID: <5683@iuvax.UUCP>
Date: 27 Jan 88 23:49:40 GMT
References: <4746@watdragon.waterloo.edu> <1430@husc2.UUCP> <686@uthub.toronto.edu> <1417@winchester.mips.COM>
Reply-To: bobmon@iuvax.UUCP (Bobmon)
Organization: Schizophrenics 'R' Us
Lines: 33


to John Mashey (whose return address didn't work) --

OK, You've confused me by the following article (exerpts from comp.sys.ibm.pc).
You seem to assume that RISC machines require relatively few clock cycles
per "vax-mip".  This would suggest that the instruction set is closely
matched to the things the benchmarks do ("vax-mip-instructions"?).

I thought that one principle of RISC was that simpler instructions could
run fast enough to allow using more of them to get the job done.  This would
mean (to me, anyway) more clocks per "vax-mip", albeit at a higher clock speed.
Would you please explain why Lower cycles/vax-mip means more RISCiness?



In article <1417@winchester.mips.COM> mash@winchester.UUCP (John Mashey) writes:
- The simplest measure of RISC-vs-CISC is the number of cycles per equivalent
- amount of work, i.e., cycles/vax-mip, for example (which is NOT the
- same as cycles/(native instruction).  The way you compute this is:
- 	...
- Rel	Clock	Clock/	Machine
- Perf	MHz	Perf	Type
- 1	5	5	VAX 11/780 [4.3BSD]
- 2.1	16.7	8	68020 (Sun-3/160)
- 4*	25	6.2	68020, 64K cache (Sun-3/260) (had to guess on this one)
- 8.4	16.7	2	SPARC (Sun-4/200) [a RISC]
- 11.3	15	1.3	MIPS R2000 (MIPS M/1000 system) [a RISC]
- 	...
- may fix that (2-cycle bus interface helps).  Notice the difference
- that the cache makes between the 2 Suns in dropping the cycle/vax-mips number.
- 
- Finally, note that even outright RISC machines differ in their
- RISCyness according to this metric.