Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!texsun!texsun.central-relay.sun.com!convex!convexc!authorplaceholder
From: hutchson@convexc.UUCP
Newsgroups: comp.arch
Subject: Re: Performance increase - a suggestion
Message-ID: <63900012@convexc>
Date: 15 Jan 88 16:24:00 GMT
References: <235@unicom.UUCP>
Lines: 9
Nf-ID: #R:unicom.UUCP:-23500:convexc:63900012:000:581
Nf-From: convexc.UUCP!hutchson    Jan 15 10:24:00 1988


A similar scheme was used on the GE-600 and its successors up to the
Honeywell DPS-70.  All memory references were double-word (72 bits);
nearly all instructions were single-word, so an instruction fetch got two
instructions.  It "worked" very well; a 600-family machine got about the
same performance as an I** 370-family machine with double the memory access
speed.  (That's raw performance, sorta like mips'es; throughput on real
multiprocessing loads was driven by other architectural details and by
OS behavior:  the GE would appear to be up to an order of magnitude faster.)