Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Performance increase - a suggestion [really RISC FP]
Message-ID: <1446@winchester.mips.COM>
Date: 31 Jan 88 01:05:48 GMT
References: <235@unicom.UUCP> <28200089@ccvaxa> <3127@phri.UUCP>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 21

In article <3127@phri.UUCP> roy@phri.UUCP (Roy Smith) writes:
>In article <28200089@ccvaxa> aglew@ccvaxa.UUCP writes:
>> I wonder how much interest might be out there for a true double-precision
>> floating point engine ....

>	Actually, I wonder if a RISC-FPP would make sense....

Made a lot of sense to us.  MIPS R2010 FPU is a single-chip RISC (+-*/, no
transcendentals) FPU, optimized heavily to make the most frequent operations go
fast in double precision.  The cycle counts are:

		SP	DP
Add/Sub		 2	 2
Multiply	 4	 5
Divide		12	19


-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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