Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!hansen From: hansen@mips.COM (Craig Hansen) Newsgroups: comp.arch Subject: Re: super multipliers Message-ID: <1483@mips.mips.COM> Date: 4 Feb 88 01:43:08 GMT References: <235@unicom.UUCP> <28200089@ccvaxa> <3127@phri.UUCP>, Lines: 27 Summary: have been around for a long time In article , jk3k+@andrew.cmu.edu (Joseph G. Keane) writes: > I've heard of a `super multiplier', a big gate-array which multiplies without > any clocking. I assume this was only integer multiplies, though. Does anyone > know if this has been done for floating point? What are the fastest times > (ns) that have been done for various multiplies? Integer multipliers in 16x16 & 32x32 sizes have been around as commercial products (usually not in gate arrays) for a while, from TRW (developed market with a burning hot bipolar chip), Weitek (first nMOS replacement part), AMD, IDT, ADI, and many others. Floating-point multipliers (and adder/subtractors) without internal latches in the computation path also exist; Weitek first introduced some fully-pipelined 32-bit parts in nMOS and later in 64-bit and CMOS, that could operate with the pipeline latches disabled (flow-through mode). IDT, AMD, ADI also have competitive parts, and BIT has a set of parts in ECL-VLSI. The fastest? Does anyone beat BIT, at 35 ns for IEEE single, 45 ns for IEEE double multiplies? This is from a preliminary data sheet, and doesn't include on-chip and off-chip delays. Disclaimer: I hold stock in some of these companies, no matter how unprofitably. -- Craig Hansen Manager, Architecture Development MIPS Computer Systems, Inc. ...{ames,decwrl,prls}!mips!hansen or hansen@mips.com 408-991-0234