Path: utzoo!utgpu!water!watmath!clyde!bellcore!decvax!ucbvax!hplabs!pyramid!voder!apple!baum
From: baum@apple.UUCP (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: conditional branches
Message-ID: <7381@apple.UUCP>
Date: 12 Feb 88 19:21:27 GMT
References: <191@telesoft.UUCP>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 26

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[]
>In <191@telesoft.UUCP> roger@telesoft.UUCP (Roger Arnold @prodigal) writes:
>What I'd like to see in an architecture, as a minimum, would be a set
>of one bit registers into which boolean values can be written.
>With addressable flag registers, conditional branch instructions could 
>directly reference the flag of interest, with no preceding test instruction.
>  Five of the flag registers could be reserved for the
>standard ALU flags (zero, negative, positive, carry, and overflow), 
>so that only one general form of conditional branch would be needed.
>
>Now, who's going to tell me that I've just described their favorite
>machine from out of the past?  Surely SOMEONE has used this idea
>before?

IBM uses exactly this scheme in the RT/PC, although they only have one
general purpose bit that can hold any boolean result. The instruction
encodings will allow conditional branches on the state of the low 16
(sometimes 8) bits of the Condition Status Register. Of these 16 bits,
9 are reserved, one is permanently 0, there are <,=,>,C,& V conditions,
and one general purpose 'test bit' that can be set with a move-to-testbit
instruction. Presumably, the reserved bits could be used for more of the
'testbits', although more  move-to-testbit instructions would be required.
Only bits in registers can be moved to/from the testbit.

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