Path: utzoo!utgpu!water!watmath!clyde!rutgers!cmcl2!husc6!mit-eddie!uw-beaver!cornell!batcomputer!itsgw!steinmetz!uunet!mfci!root
From: root@mfci.UUCP (SuperUser)
Newsgroups: comp.arch
Subject: Re: 432
Message-ID: <280@m2.mfci.UUCP>
Date: 12 Feb 88 17:08:50 GMT
References: <277@m2.mfci.UUCP>
Reply-To: mfci!colwell@uunet.UUCP (Robert Colwell)
Organization: Multiflow Computer Inc., Branford Ct. 06405
Lines: 25

I need to correct something I posted a few weeks back about the Intel
432.  In response to something Howard Landman wrote, I implied that
there was nothing architecturally preventing the 432 from achieving
acceptable performance, and blamed everything on the implementation.

At the time I was thinking of the usual litany of sins people think
of in conjunction with the 432 (7-level addressing, complex instruction
set).  But I overstated my case -- there were some architectural
errors too, such as providing no general data registers (only 16 bits
worth of the top-of-stack were on-chip), and providing no
instruction-stream literals except 0 and 1.

The lack of general registers was the reason that the instruction
object code size was not gratifyingly small (which was the whole
reason for a bit-aligned instruction set to begin with).

Remember, though, that the implementation errors that were made in the
432 were independent of its being a CISC or being capability-based.

There.  Now I've assuaged my guilty conscience.

Bob Colwell            mfci!colwell@uunet.uucp
Multiflow Computer
175 N. Main St.
Branford, CT 06405     203-488-6090