Path: utzoo!utgpu!water!watmath!clyde!rutgers!gatech!hao!ames!pasteur!ucbvax!hplabs!pyramid!prls!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <1585@winchester.mips.COM>
Date: 16 Feb 88 16:13:26 GMT
References: <191@telesoft.UUCP> <1556@gumby.mips.COM> <208@telesoft.UUCP> <7405@apple.UUCP> <6834@sol.ARPA>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 24

In article <6834@sol.ARPA> crowl@cs.rochester.edu (Lawrence Crowl) writes:
>Several authors have been arguing over conditional branching using condition
>codes versus using booleans in general-purpose registers.  Why not store the
>condition codes in a general-purpose register?  ....

>    compare R1 with R2 place condition code in R3
>    branch to ADDRESS if condition code in R3 is GREATER
>    branch to ADDRESS if condition code in R3 is EQUAL
>    branch to ADDRESS if condition code in R3 is LESS

>Will this approach work?  Will the condition code comparison in the branch cost
>too much?  (It is an instruction constant.)  Comments please!

In some flavor or other, at least several RISCs do this,
such as:
	MIPS R2000  (has set-less-than op that generates 0 or 1)
	AMD 29000 (has compare insts that set sign bit of arb. reg)
	Moto 78000 (has compares that set cond codes in regs, I think)
and I think HP Precision does this also.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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