Path: utzoo!utgpu!water!watmath!clyde!rutgers!cbmvax!daveh From: daveh@cbmvax.UUCP (Dave Haynie) Newsgroups: comp.sys.amiga Subject: Re: Still More 68020 Questions Message-ID: <3248@cbmvax.UUCP> Date: 1 Feb 88 23:58:17 GMT References: <2769@omepd> Organization: Commodore Technology, West Chester, PA Lines: 37 in article <2769@omepd>, hah@mipon3.intel.com (Hans Hansen) says: > In article <3204@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes: > $in article <9750@ccicpg.UUCP>, harald@ccicpg.UUCP ( Harald Milne) says: > $> Now the question is, is there a signal present that indicates > $> CHIP/FAST ram access? > $> Is it present on the A2000 MMU conector? > $Basically. To detect CHIP RAM for any CPU cycle, look at A23, A22, and A21. > $Are they all 0. Yes? You're accessing CHIP RAM. No? Not in CHIP RAM. > $ > Not completely true. In the context of cache consistency, that IS completely true. And that's what this thread is about, eh? What's that they say about questioning wizards.... > The A500 and B2000 are inserting the additional 512K of RAM inside of the > CHIP memory port and it must be addressed with the same constraints as CHIP > RAM. EXCEPT for things that relate to custom chip operation. Like cache consistency. You don't your data cache to cache CHIP RAM, because something like a BLIT or some floppy disk DMA will write to it. Only, from the point of view of the rest of the system, you're never sure when that writing will take place. So you don't cache any of it. Agnus can't write to $C00000 memory any more than she can write to the first Fast RAM card you've got sitting autoconfigured at $200000. So the only rules you have follow in dealing with cache consistency are those you apply to system/expansion bus DMA. The $C00000 RAM looks exactly like Fast RAM in this case. > Hans hah@inteloa.UUCP -- Dave Haynie "The B2000 Guy" Commodore-Amiga "The Crew That Never Rests" {ihnp4|uunet|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy "I can't relax, 'cause I'm a Boinger!"