Path: utzoo!mnetor!uunet!husc6!bbn!oberon!bloom-beacon!gatech!hao!noao!mcdsun!nud!rover!mph
From: mph@rover.UUCP (Mark Huth)
Newsgroups: comp.sys.amiga
Subject: Re: 68030, cacheing, DMA devices
Message-ID: <761@rover.UUCP>
Date: 5 Feb 88 20:55:54 GMT
References: <8179@g.ms.uky.edu>
Reply-To: mph@rover.UUCP (Mark Huth)
Organization: Motorola Microcomputer Division, Tempe, Az.
Lines: 28

In article <8179@g.ms.uky.edu> sean@ms.uky.edu (Sean Casey) writes:
>
>The problem that people have brought up is that a DMA device
>will screw up a system running a data cache.  Since the 68030
>has an onboard data cache, enabling it would screw up things for
>an Amiga, which has several DMA devices.
>
>It seems to me that the chip designers would have considered this.  *I*
>would have considered it.  Surely the onboard MMU can be told that certain
>pages of memory are not to be cached.  Could someone who has the specs
>for the processor check this out?

I've got the specs, and the chip designers did think of this problem.
The MMU is basically a subset of the 68851 MMU chip.  One of the
fields in the translation structure is a cache inhibit bit.  The
value of this bit is output to a cache inhibit output to allow the MMU
to inhibit external caches.  The internal caches are also inhibitted by
this field.  Sooo.. the exec should set up the MMU translation tables
to inhibit caching of any memory that might be the target of writes by
other bus masters.

Additionally, there is a cache inhibit input to the 68030.  This
allows external hardware to inhibit caching on a cycle by cycle basis.
This all leads to the conclusion that the 68030 will work in a
multi-master system.  Now whether it will really work in the Amiga
remains to be seen.

Mark Huth