Path: utzoo!utgpu!water!watmath!clyde!bellcore!decvax!decwrl!granite!jmd
From: jmd@granite.dec.com (John Danskin)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <184@granite.dec.com>
Date: 17 Feb 88 17:09:12 GMT
References: <191@telesoft.UUCP> <1556@gumby.mips.COM> <208@telesoft.UUCP> <7405@apple.UUCP> <6834@sol.ARPA> <3798@lll-winken.llnl.gov>
Reply-To: jmd@granite.UUCP (John Danskin)
Organization: DEC Workstation Systems Engineering
Lines: 47

I am a fan of condition codes in general registers because I would like to be
able to turn the following code sequence:

	fcmp	r0, r1
	nop
	nop
	br	GE, somewhere

	fcmp	r0, r2
	nop
	nop
	br	GE, somewhere1

	fcmp	r0, r3
	nop
	nop
	br	GE, somewhere2

into
	fcmp	r0, r1, c1
	fcmp	r0, r2, c2
	fcmp	r0, r3, c3

	br	GE, c1, somewhere
	br	GE, c2, somewhere2
	br	GE, c3, somewhere3

Obviously two operand compare and branch is niftier, but hardly anyone can
do that in one (reasonably fast) risc cycle.

I have no idea how much this sort of thing comes up in average code,
but it makes a fair bit of difference in 3D graphics clipping computations.

I would like to say as well that it seems like a waste to put the condition
codes in GENERAL registers. The little suckers are only one or two bits
depending on how you set things up, and it would be relatively inexpensive
to have a whole bank of special condition code registers. Some vector
instruction sets do this already.

Anybody care to flame on how incredibly useless this is for the real world?
After all, I make MY living writing microcode, and we all know that nobody
has been doing that since 1843 8-).
-- 
John Danskin				| decwrl!jmd
DEC Workstation Systems Engineering	| (415)853-6724 
100 Hamilton Avenue			| My comments are my own.
Palo Alto, CA  94306			| I do not speak for DEC.