Path: utzoo!utgpu!water!watmath!clyde!bellcore!decvax!ucbvax!hplabs!pyramid!voder!apple!baum
From: baum@apple.UUCP (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <7430@apple.UUCP>
Date: 18 Feb 88 00:05:29 GMT
References: <191@telesoft.UUCP> <1556@gumby.mips.COM> <208@telesoft.UUCP> <7405@apple.UUCP> <6834@sol.ARPA> <1585@winchester.mips.COM>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 19

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[]
>In article <1585@winchester.mips.COM> mash@winchester.UUCP(John Mashey)writes:
re: conditional branching using condition codes vs. booleans in GPRs:
>
>In some flavor or other, at least several RISCs do this, such as:
....
>and I think HP Precision does this also.

HP does have {Compare,Move,Bittest,Add}&Branch instructions. It can't set an
arbitrary condition in any bit of a register in one instruction; however, there
is a special instruction (compare&clear) that allows construction of a 2
instruction sequence that will; it can also be used for other things, since
the instruction following compare&clear (it 'skips' on condition) can be any
instruction, not just the obvious 'load immediate 1'. There was a load 
condition inst. at one time, but it was removed because it looked like it added
a gate to the critical path length.

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