Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!earl
From: earl@mips.COM (Earl Killian)
Newsgroups: comp.arch
Subject: Re: conditional branches
Message-ID: <1556@gumby.mips.COM>
Date: 12 Feb 88 01:53:39 GMT
References: <191@telesoft.UUCP>
Lines: 18
In-reply-to: roger@telesoft.UUCP's message of 11 Feb 88 01:06:57 GMT


Roger Arnold proposes that branches be implemented as computing
booleans (to one of 32 1-bit homes to be specific) and testing them in
a separate instruction, for the the purpose of optimizing tests.

The problem with this is that it makes a conditional a two instruction
sequence.  With what we know about instruction frequencies, this is
not a good idea.  The abstract concept of "compare two values and
branch accordingly" represents around 15% of the instructions executed
on a computer.  To make this take two instructions increases your
instruction count by 15% (and thus, in many cases, your cycle count by
15%).

Packaging the abstract concept of conditional branching into one
instruction rather than two is one of the numerous ways that some RISC
machines go faster than other architectures.  What I've found quite
surprizing is that some recent architectures (e.g. Berkeley RISC and
its clone, SPARC), used condition codes after studying instruction
stream statistics.  I suppose compare and branch in one instruction
was considered too difficult, at the time.