Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!decwrl!labrea!rutgers!sunybcs!bingvaxu!leah!itsgw!imagine!pawl1.pawl.rpi.edu!jesup From: jesup@pawl1.pawl.rpi.edu (Randell E. Jesup) Newsgroups: comp.arch Subject: Re: conditional branches Message-ID: <375@imagine.PAWL.RPI.EDU> Date: 16 Feb 88 08:39:17 GMT References: <191@telesoft.UUCP> <1556@gumby.mips.COM> Sender: news@imagine.PAWL.RPI.EDU Reply-To: beowulf!lunge!jesup@steinmetz.UUCP Organization: RPI Public Access Workstation Lab - Troy, NY Lines: 35 In article <1556@gumby.mips.COM> earl@mips.COM (Earl Killian) writes: >Roger Arnold proposes that branches be implemented as computing >booleans (to one of 32 1-bit homes to be specific) and testing them in >a separate instruction, for the the purpose of optimizing tests. ... >Packaging the abstract concept of conditional branching into one >instruction rather than two is one of the numerous ways that some RISC >machines go faster than other architectures. What I've found quite >surprizing is that some recent architectures (e.g. Berkeley RISC and >its clone, SPARC), used condition codes after studying instruction >stream statistics. I suppose compare and branch in one instruction >was considered too difficult, at the time. Think about compare & branch from a hardware point of view. To do it in one cycle, you must fetch two values, run them through the ALU, and get the result. Now you have the information that allows you to determine whether to branch. You must also determine the branch destination. This may also require some computation, an addition to the PC (though it might be speeded a little by knowing the offset if some small number of bits, which it has to be given a 32-bit instruction.) If you're willing to build another fast adder for this computation and run it in parallel, you MIGHT be able to pull it off, though I doubt it. It would cost LOTS of chip area, and would probably be your critical path that determines your cycle time (certainly it would be if you didn't have a parallel adder!) I'm not saying that conditions codes are the answer, just that the one- instruction compare & branch creates some big problems for chip designers at the hardware level. If you go to the ISSCC (?), check out the solution that the GE RPM-40 uses (not that it's perfect either). More I think I should not say before the conference. // Randell Jesup Lunge Software Development // Dedicated Amiga Programmer 13 Frear Ave, Troy, NY 12180 \\// beowulf!lunge!jesup@steinmetz.UUCP (518) 272-2942 \/ (uunet!steinmetz!beowulf!lunge!jesup) BIX: rjesup