Path: utzoo!utgpu!water!watmath!ccplumb
From: ccplumb@watmath.waterloo.edu (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <17031@watmath.waterloo.edu>
Date: 21 Feb 88 16:34:57 GMT
References: <6834@sol.ARPA> <780004@otter.hple.hp.com>
Reply-To: ccplumb@watmath.waterloo.edu (Colin Plumb)
Organization: U of Waterloo, Ontario
Lines: 43
Confusion: U. of Waterloo, Ontario

kers@otter.hple.hp.com (Christopher Dollin) wrote:
>The critical points about the ARM from this point of view are (a) it is based
>on condition codes rather than compare-and-branch; (b) the register operations 
>set the CCs *optionally*; (c) *every* instruction is conditional, so some IF
>statements can be implemented with no branching at all; for example
>
>    abs(x) -> x
>
>can be implemented as
>
>    TEQ     x, #0       ; tell me about (register) x 
>    RSBMI   x, #0       ; if it's <0 then 0-x -> x (reverse subtract)
>
>Your turn guys ......................

Well, something similar can be done with result flags in general-purpose
registers.  For example, if the Am29000 used -1 for true instead of
80000000, you could do that in three instructions:

cplt	temp, x, #0	; temp = (x < 0)
xor	x, x, temp	; x ^= temp;
sub	x, x, temp	; x -= temp

If temp is 0 after the test, this has no effect on x, but if
it's -1, this inverts x and adds one, i.e. negates it.

The 29000 doesn't quite do things this way, but isn't there a processor
out there somewhere that does?

Things like z = (x > y) ? a : b; become three instructions:
cpgt	z, x, y		; z = (x > y)	/* z now holds 0 or -1	*/
and	z, z, #a-b	; z &= (a-b)	/* z now holds 0 or a-b */
add	z, z, #b	; z += b	/* z now holds b or a	*/

In this case, the ARM can do no better, although it seems that it can
in the general case.  As pipelines grow longer, we may see skip
instructions come back.  They may "waste" a cycle on a no-op, but they
keep the pipeline full.
--
	-Colin (watmath!ccplumb)

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