Path: utzoo!utgpu!water!watmath!clyde!rutgers!cmcl2!beta!hc!ames!amdahl!nsc!amos From: amos@nsc.nsc.com (Amos Shapir NSTA) Newsgroups: comp.arch Subject: Re: RISC data alignment Message-ID: <4976@nsc.nsc.com> Date: 20 Feb 88 17:39:13 GMT References: <2635@calmasd.GE.COM> <28200092@ccvaxa> <496@ecrcvax.UUCP> <3001@bloom-beacon.MIT.EDU> <2047@rti.UUCP> Organization: National Semiconductor, Sunnyvale Lines: 18 In article <2047@rti.UUCP> mcm@rti.UUCP (Mike Mitchell) writes: >I have written device drivers where I created a structure to hold >the memory-mapped status registers. Some of the hardware had very >strange memory alignments, and if the structure elements were changed, >the driver would break. This is not a very good example - the CPU reading the structure (i.e. the device controller) is not the same as the one you compile for, and therefore you cannot assume compatibility. It is true, though, that C is generally a what-you-see-is-what-you-get language, and most C programmers have come to expect - but this is more of a side-effect than a feature. -- Amos Shapir My other CPU is a NS32532 National Semiconductor 7C/266 1135 Kern st. Sunnyvale (408) 721-8161 amos@nsc.com till March 1, 88; Then back to amos%taux01@nsc.com