Path: utzoo!utgpu!water!watmath!clyde!rutgers!ucsd!sdcsvax!ucsdhub!hp-sdd!hplabs!nsc!pauls
From: pauls@nsc.nsc.com (Paul Sweazey)
Newsgroups: comp.arch
Subject: Re: Self timed processors (was Re: Cycle stretching)
Message-ID: <4979@nsc.nsc.com>
Date: 21 Feb 88 19:29:17 GMT
References: <844@daisy.UUCP> <20409@amdcad.AMD.COM> <1232@alliant.Alliant.COM> <810@spar.SPAR.SLB.COM>
Reply-To: pauls@nsc.UUCP (Paul Sweazey)
Organization: National Semiconductor, Sunnyvale
Lines: 13

Although asynchronous computing is attractive, it isn't likely to be
commercially attempted until a production VLSI design methodology
exist that synthesized asynchronous state machines that are correct
by construction, and that analyzes them to eliminate the races and
hazards, without also eliminating the performance advantages.

If someone out there is qualified to build such tools, send me email.

Paul Sweazey,  M/S D3678
National Semiconductor Corporation
2900 Semiconductor Drive, PO Box 58090
Santa Clara, CA 95052		Work: 408-721-5860
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