Path: utzoo!mnetor!uunet!husc6!bloom-beacon!gatech!mcnc!ncsuvx!lll-winken!lll-crg.llnl.gov!brooks
From: brooks@lll-crg.llnl.gov (Eugene D. Brooks III)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <3798@lll-winken.llnl.gov>
Date: 16 Feb 88 23:56:17 GMT
References: <191@telesoft.UUCP> <1556@gumby.mips.COM> <208@telesoft.UUCP> <7405@apple.UUCP> <6834@sol.ARPA>
Sender: usenet@lll-winken.llnl.gov
Reply-To: brooks@lll-crg.llnl.gov.UUCP (Eugene D. Brooks III)
Organization: Lawrence Livermore National Laboratory
Lines: 33

In article <6834@sol.ARPA> crowl@cs.rochester.edu (Lawrence Crowl) writes:
>Several authors have been arguing over conditional branching using condition
>codes versus using booleans in general-purpose registers.  Why not store the
>condition codes in a general-purpose register?  This would result in a
>scheduable two-instruction sequence with multi-way branching at the cost of
>using a general purpose register and slightly lower code density.  For example,
>
>    compare R1 with R2 place condition code in R3
>    branch to ADDRESS if condition code in R3 is GREATER
>    branch to ADDRESS if condition code in R3 is EQUAL
>    branch to ADDRESS if condition code in R3 is LESS
>
>Will this approach work?  Will the condition code comparison in the branch cost
>too much?  (It is an instruction constant.)  Comments please!
Yes, it works.  An example of such an engine is the Ridge 32 manufactured
by Ridge Computers Inc., of Santa Clara, CA.  No only are there instructions
to put a "condition code" in a register, there are instructions to conditional
branch with the registers involved in the comparison direction.  For example:
branch if the value in R1 is greater than the value in R2, along with a
branch prediction bit as well.  The branch takes one clock if the prediction
is correct, 4 clocks if it the prediciton bit is wrong.  It worketh, and it
worketh well.

There is a very BIG lesson here as well for those who are picking an instruction
set to "simulate".  RISC is the way to fly, but in addition one finds that the
cost of computing condition codes can be far greater than the cost of computing
the results of an instruction itself, only to either ignore the condition codes
or destroy them in the next instruction.

Choosing an instruction set with "no condition codes" is a major kick in the
butt with respect to simulator speed.  This is one of the key reasons why
the Ridge 32 instruction set, suitably generalized for the purposes of the
shared memory multiprocessor environment, was chosen for the Cerberus
multiprocessor simulator.