Path: utzoo!utgpu!water!watmath!clyde!rutgers!cmcl2!nrl-cmf!ames!ucsd!sdcsvax!ucsdhub!hp-sdd!hplabs!decwrl!spar!malcolm
From: malcolm@spar.SPAR.SLB.COM (Malcolm Slaney)
Newsgroups: comp.arch
Subject: Re: Self timed processors (was Re: Cycle stretching)
Summary: Southerland and Sproul have the tools
Message-ID: <822@spar.SPAR.SLB.COM>
Date: 21 Feb 88 21:37:36 GMT
References: <844@daisy.UUCP> <20409@amdcad.AMD.COM> <1232@alliant.Alliant.COM> <810@spar.SPAR.SLB.COM> <4979@nsc.nsc.com>
Reply-To: malcolm@spar.slb.com (Malcolm Slaney)
Organization: SPAR - Schlumberger Palo Alto Research
Lines: 17

In article <4979@nsc.nsc.com> pauls@nsc.UUCP (Paul Sweazey) writes:
>Although asynchronous computing is attractive, it isn't likely to be
>commercially attempted until a production VLSI design methodology
>exist that synthesized asynchronous state machines that are correct
>by construction, and that analyzes them to eliminate the races and
>hazards, without also eliminating the performance advantages.
>
>If someone out there is qualified to build such tools, send me email.

I think that Bob Sproul (of CMU) and Ivan Southerland (as in the graphics
company) have the methodology down.  I attended a short course they taught 
on their ideas last year and while the stuff is messy it does seem to work.
Their ideas were written up in Electronics last year.

Cheers.

							Malcolm