Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!amdcad!ames!necntc!linus!alliant!lackey
From: lackey@Alliant.COM (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Cycle stretching
Message-ID: <1232@alliant.Alliant.COM>
Date: 17 Feb 88 17:29:19 GMT
References: <844@daisy.UUCP> <20409@amdcad.AMD.COM>
Reply-To: lackey@alliant.UUCP (Stan Lackey)
Organization: Alliant Computer Systems, Littleton, MA
Lines: 16

>In article <844@daisy.UUCP> david@daisy.UUCP (David Schachter) writes:
>>
>>Say I have a CPU where 99 percent of the instructions
>>take, say, one clock.  The remaining instructions need just a little longer--
>>one clock plus a few nanoseconds.  Why not stretch the clock a bit when exec-
>>uting those instructions, instead of wasting most of a second clock period?

Actually, I once heard a proposal to make a microprocessor totally 
ansynchronous, with logic added to determine when each stage of logic was
complete, and use that to start the next stage.  It would take advantage of
the fact that an ALU might be done sooner when adding small numbers, and lots
of times the numbers added are small (compared to the total size of the 
data path).  "Self-timed" is what it was called.

An interesting idea, but likely wouldn't work too well in a pipeline, and
would be difficult to interface to.  -Stan