Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!quintus!ok
From: ok@quintus.UUCP (Richard A. O'Keefe)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <662@cresswell.quintus.UUCP>
Date: 19 Feb 88 03:18:57 GMT
References: <191@telesoft.UUCP> <1556@gumby.mips.COM> <208@telesoft.UUCP> <184@granite.dec.com>
Organization: Quintus Computer Systems, Mountain View, CA
Lines: 20

In article <184@granite.dec.com>, jmd@granite.dec.com (John Danskin) writes:
> I would like to say as well that it seems like a waste to put the condition
> codes in GENERAL registers. The little suckers are only one or two bits
> depending on how you set things up, and it would be relatively inexpensive
> to have a whole bank of special condition code registers. Some vector
> instruction sets do this already.
> 
What's wrong with putting the condition codes in general registers?
If you have as many registers as taking a RISC is supposed to buy you,
putting a condition code in a general register isn't going to hurt,
and there is an interesting advantage.  Having the conditional
branches be of the form
	B<cc> <reg>,<label>
means that you have a fast way of dispatching on some combinations of
bits in a register, which means dispatching on tag bits can be *faster*
than it would in a condition-code architecture.  It also means that if
you want to set up a particular set of conditions (e.g. clearing the
carry before starting a multi-precision add) you just use an ordinary
constant->register move, and don't need a special class of instructions
for setting condition registers.