Path: utzoo!mnetor!uunet!husc6!mit-eddie!uw-beaver!cornell!rochester!PT.CS.CMU.EDU!K.GP.CS.CMU.EDU!lindsay
From: lindsay@K.GP.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: target caching
Message-ID: <910@PT.CS.CMU.EDU>
Date: 20 Feb 88 02:56:19 GMT
Sender: netnews@PT.CS.CMU.EDU
Organization: Carnegie-Mellon University, CS/RI
Lines: 31
Keywords: page mode

The TF-1 people at IBM intend to use an interesting trick to simplify their
CPU.

DRAMs can be purchased that have "page mode" - that is, you can access the
next-address value much more quickly than a randomly addressed value.  This
is because each random access can leave a large number of bits in a long
register (say, 1024 bits, in the case of a 1Mb RAM). A page-mode access just
shifts the register. 

So, the TF-1 CPU chip will expect another 32 bits of instruction every 20ns.
As long as the PC just upcounts, they claim that page-mode RAMs will be fast
enough.

When the CPU decides to branch, of course, there's trouble. They solve this
by keeping a cache of the instruction streams at 32 recent branch targets.
If the target PC hits, then they fetch instructions from the cached stream,
until the RAMs have done their random access, and are ready to page-mode
again.

I haven't studied the recent RAM offerings well enough to count the cycles,
and critique the speed expectations. I guess it sounds fine, and it does
sound simple. But, there's a major catch: it's a Harvard architecture.  The
memory is code-only, so that grubby data won't spoil the code's pipelined
perfection.

I know that some recent RAM chips are dual-ported, supposedly so that a
processor can write image data through the random port, while a graphics
screen is being refreshed through the page-mode port. Would these chips
allow the TF-1 trick to work in non-Harvard designs ? 
-- 
	Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science