Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!mordor!sri-spam!ames!ucsd!sdcsvax!ucsdhub!hp-sdd!hplabs!otter!kers
From: kers@otter.hple.hp.com (Christopher Dollin)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <780004@otter.hple.hp.com>
Date: 19 Feb 88 15:14:59 GMT
References: <6834@sol.ARPA>
Organization: Hewlett-Packard Laboratories, Bristol, UK.
Lines: 20

In view of this discussion on the merits or otherwise of condition codes,
especially as applied to RISCy machines, I wonder what the assembled multitudes
think about the architecture of the Acorn Risc Machine (ARM)?

The critical points about the ARM from this point of view are (a) it is based
on condition codes rather than compare-and-branch; (b) the register operations 
set the CCs *optionally*; (c) *every* instruction is conditional, so some IF
statements can be implemented with no branching at all; for example

    abs(x) -> x

can be implemented as

    TEQ     x, #0       ; tell me about (register) x 
    RSBMI   x, #0       ; if it's <0 then 0-x -> x (reverse subtract)

Your turn guys ......................


Regards,
Kers                                    | "Why Lisp if you can talk Poperly?"