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From: kyriazis@pawl11.pawl.rpi.edu (George Kyriazis)
Newsgroups: comp.arch
Subject: Re: Cycle stretching
Message-ID: <393@imagine.PAWL.RPI.EDU>
Date: 20 Feb 88 05:27:30 GMT
References: <844@daisy.UUCP> <20409@amdcad.AMD.COM> <1232@alliant.Alliant.COM>
Sender: news@imagine.PAWL.RPI.EDU
Reply-To: kyriazis@pawl11.pawl.rpi.edu (George Kyriazis)
Organization: RPI Public Access Workstation Lab - Troy, NY
Lines: 44
Summary: Cycle streching, self-timed circuits and dataflow computers

In article <1232@alliant.Alliant.COM> lackey@alliant.UUCP (Stan Lackey) writes:
>>In article <844@daisy.UUCP> david@daisy.UUCP (David Schachter) writes:
>>>
>>>Say I have a CPU where 99 percent of the instructions
>>>take, say, one clock.  The remaining instructions need just a little longer-
>>>one clock plus a few nanoseconds...
>
>Actually, I once heard a proposal to make a microprocessor totally 
>ansynchronous, with logic added to determine when each stage of logic was
>complete, and use that to start the next stage.  It would take advantage of
>the fact that an ALU might be done sooner when adding small numbers, and lots
>of times the numbers added are small (compared to the total size of the 
>data path).  "Self-timed" is what it was called.

  Yes.  There is a chapter in Mead-Conway's book 'Introduction to VLSI Systems'
describing self-timed circuits.  The concept is pretty interesting, since (for
example) a circuit can be built using self-timed circuits and the interface
can be built to communicate with normal clocke circuitry.  It starts beeing
interesting when you realize that if you want to make the chip (or the CPU)
faster, you can just lower the temperature... No adjustable clocks, no nothing.

>
>An interesting idea, but likely wouldn't work too well in a pipeline, and
>would be difficult to interface to.  -Stan

  Yes, interfacing is more difficult, but there are standard ways to overcome
the difficulty.  The problem is elsewhere.  Since there cannot be a BUS ENABLE
signal for internal buses (you will have to wait for the last signal to change
state before you toggle ENABLE), the only solution is to have 2 wires for every
bit.  One to say 'ok, I have a 1' and another one saying 'ok, I have a 0'.
That doubles the amount of wires required for every datapath, thing that
can easily lower the transistor density of the chip.
  Another interesting thing about self-timed circuits is that they look that
they have a lot of things in common with the pronciples used in Dataflow
computers, like 'This operation won't be executed unless I get results from
"there" and "there"'.


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*George C. Kyriazis                                   *    Gravity is a myth
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