Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!hao!gatech!purdue!i.cc.purdue.edu!j.cc.purdue.edu!pur-ee!uiucdcs!uiucdcsm!grunwald
From: grunwald@uiucdcsm.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: Cycle stretching
Message-ID: <3300016@uiucdcsm>
Date: 19 Feb 88 06:11:00 GMT
References: <844@daisy.UUCP>
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Nf-ID: #R:daisy.UUCP:844:uiucdcsm:3300016:000:741
Nf-From: uiucdcsm.cs.uiuc.edu!grunwald    Feb 19 00:11:00 1988


There is a recent tech report from CalTech discussing synthesis of self
time circuits. CalTech has historically promoted the use of self-timed
circuitry for reliability. Heretofore, the main problems have been
design complexity.

As an example, the AMRD (Async. Message Routing Device) of the Ametek 2010
machien uses a self-timed network. When I saw the machine, they had 1/2 the
parts running at 8Mhz (I think) & the other half at 12Mhz. They wanted to
get to 20Mhz eventually. However, the key point is that when you communicated
between the 12Mhz parts, you ran at 12Mhz. The 12Mhz parts only ran at 8Mhz
when there was an 8Mhz part in the chain.  As long as the complexity is
managable, it certainly appears to be a good design method.