Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!ucsd!sdcsvax!ucsdhub!hp-sdd!hplabs!hpda!hpcupt1!viggy
From: viggy@hpcupt1.HP.COM (Viggy Mokkarala)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Registers
Message-ID: <6310004@hpcupt1.HP.COM>
Date: 19 Feb 88 18:09:11 GMT
References: <6834@sol.ARPA>
Organization: Hewlett Packard, Cupertino
Lines: 31

In article <7430@apple.UUCP> baum@apple.UUCP (Allen J. Baum) writes:


>HP does have {Compare,Move,Bittest,Add}&Branch instructions. It can't set an
>arbitrary condition in any bit of a register in one instruction; however, there
>is a special instruction (compare&clear) that allows construction of a 2
>instruction sequence that will; it can also be used for other things, since
>the instruction following compare&clear (it 'skips' on condition) can be any
>instruction, not just the obvious 'load immediate 1'. There was a load 
>condition inst. at one time, but it was removed because it looked like it added
>a gate to the critical path length.

>{decwrl,hplabs,ihnp4}!nsc!apple!baum		(408)973-3385

Thanks Allen, for pointing this out.  At the risk of restating facts, I want to
elaborate on the Compare and Clear instruction (for those who don't have a HPPA
handbook).

The Compare and Clear instruction compares two registers, clears a register,
and conditionally nullifies the execution of the following instruction (based
on the result of the comparison).  There are 16 conditions that can be tested
against.

This instruction can be used to produce, in a general register, the logical
value (0 or 1) of the result of a comparison.

The two instruction sequence

	COMCLR, <>	rb, rc, ra
	LDO		1(0),ra

sets ra to 1 if rb and rc are equal and to 0 otherwise.