Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!voder!apple!bcase
From: bcase@apple.UUCP (Brian Case)
Newsgroups: comp.arch
Subject: Re: target caching
Message-ID: <7456@apple.UUCP>
Date: 22 Feb 88 01:22:56 GMT
References: <910@PT.CS.CMU.EDU> <20482@amdcad.AMD.COM>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc., Cupertino, USA
Lines: 14
Keywords: page mode

In article <20482@amdcad.AMD.COM> tim@amdcad.UUCP (Tim Olson) writes:
>In article <910@PT.CS.CMU.EDU> lindsay@K.GP.CS.CMU.EDU (Donald Lindsay) writes:
>| When the CPU decides to branch, of course, there's trouble. They solve this
>| by keeping a cache of the instruction streams at 32 recent branch targets.
>| If the target PC hits, then they fetch instructions from the cached stream,
>| until the RAMs have done their random access, and are ready to page-mode
>| again.
>
>Wow!  Either there is serendipity involved here, or the TF-1 architects
>closely studied the Am29000 Manual -- this is the exact method we use to
>keep the pipeline fed during branches -- even the number of entries is
>the same!

And by the way, AMD has a patent pending on this (Phil Frieden's name leads
the list; thanks Phil!  (hope I spelled your last name right!)).