Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!voder!apple!bcase
From: bcase@apple.UUCP (Brian Case)
Newsgroups: comp.arch
Subject: Re: conditional branches
Message-ID: <7457@apple.UUCP>
Date: 22 Feb 88 01:34:34 GMT
References: <191@telesoft.UUCP> <1556@gumby.mips.COM> <375@imagine.PAWL.RPI.EDU> <1610@gumby.mips.COM> <400@imagine.PAWL.RPI.EDU>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc., Cupertino, USA
Lines: 13

In article <400@imagine.PAWL.RPI.EDU> beowulf!lunge!jesup@steinmetz.UUCP writes:
>In article <1610@gumby.mips.COM> earl@mips.COM (Earl Killian) writes:
>>In article <375@imagine.PAWL.RPI.EDU> jesup@pawl1.pawl.rpi.edu (Randell E. Jesup) writes:
> A full ALU (which is just an adder and a shifter) can take
>20+% of the entire chip.  The bigger the chip, the lower the yield, and
>the more delays in intra-chip runs.

WOW!  What technology are you talking about?  Looking at the die photo of
the 29K (1.25 micron CMOS), the ALU/shifter is between 5% and 7% of the
die.  The PC+relative offset adder is probably more like 3%.  Eliminating
the PC adder would probably have had no effect on the yield-influencing
die size (although this analysis does not include internal bus considerations;
but I would guess that sharing the main ALU for PC+offset would have
*increased* the internal bus overhead).