Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!voder!apple!bcase
From: bcase@apple.UUCP (Brian Case)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC
Message-ID: <7464@apple.UUCP>
Date: 22 Feb 88 19:21:40 GMT
References: <1642@mips.mips.COM>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc., Cupertino, USA
Lines: 23
Keywords: General Electric, DARPA-MIPS-core-ISA

In article <1642@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>
>   
>Several articles have recently appeared, alluding to a CMOS  uP
>built by General Electric, e.g. <9629@steinmetz.steinmetz.UUCP>,
><9631@steinmetz.steinmetz.UUCP>, and <375@imagine.PAWL.RPI.EDU>.
>
>Branch instructions _seem_ to have only a 12-bit displacement field;
>there doesn't appear to be a "Branch Register", "Branch And Link",
>or "Conditional Branch" instruction.  Perhaps the "COND" instruction
>is the conditional-skip instruction recently mentioned on the net**.

Allen Baum (who attended the conference) told me that the single branch
instruction is only available in the conditional form.  Thus, for
an unconditional branch, you must make sure that you know the state of
the single boolean bit (compares test a condition and set the state of
the boolean bit).

>11. A simple virtual memory scheme called "most significant bit replacement"
>    is used.  A process-id is appended to the MSB's of an address before
>    sending it out of the CPU.  A special case occurs when those bits
>are all-0's or all-1's.... ** **

Isn't this the original Stanford MIPS scheme?