Path: utzoo!mnetor!uunet!husc6!hao!oddjob!gargoyle!ihnp4!alberta!calgary!radford
From: radford@calgary.UUCP (Radford Neal)
Newsgroups: comp.arch
Subject: Auto-shifted registers
Message-ID: <1370@vaxb.calgary.UUCP>
Date: 20 Feb 88 23:06:04 GMT
Organization: U. of Calgary, Calgary, Ab.
Lines: 35

Several instruction sets, such as the 68020 and the VAX, have
an "indexed" addressing mode, in which a register is shifted 
left by 0, 1, 2, or 3 bits before being added to a displacement,
allowing easy access to arrays of ints, etc.

I has occurred to me that this "auto-shifting" might be useful
for ALL register references. Every reference to a register as
a source operand would be accompanied by two bits giving a
shift amount - equivalet to a multiplication by 1, 2, 4, or 8.

This gets you indexed addressing for no extra work, given
register-offset addressing. It also lets you do various
other operations quickly. For example:

   add r1 = 2*r2+8*r2   Calculates 10*r2 in a single instruction
   
   add r1 = 2*r1+r2     Shifts a bit into the bottom r1

(I assume here an instruction set with three-address, register-to-
register instructions, a la the CDC 6600.)

Speaking from a position of marginal hardware literacy, it seems
to me that the shifting might be done in parallel with the
register address decode. The data path out of the register
bank would contain a one-bit shifter and a two-bit shifter (essentially
a very small barell-shifter). While the register address is
being decoded, the decision as to whether the data is shifted
in either of these two shifters is being made also. When the
data comes out of the register, it propagates through the
two shifters at close to the speed of light.

Anyone want to comment on this idea?

   Radford Neal
   The University of Calgary