Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!decwrl!granite!jmd
From: jmd@granite.dec.com (John Danskin)
Newsgroups: comp.arch
Subject: Re: Auto-shifted registers
Message-ID: <188@granite.dec.com>
Date: 23 Feb 88 17:52:07 GMT
References: <1370@vaxb.calgary.UUCP>
Reply-To: jmd@granite.UUCP (John Danskin)
Organization: DEC Workstation Systems Engineering
Lines: 32

In article <1370@vaxb.calgary.UUCP> radford@calgary.UUCP (Radford Neal) writes:
>Several instruction sets, such as the 68020 and the VAX, have
>an "indexed" addressing mode, in which a register is shifted 
>left by 0, 1, 2, or 3 bits before being added to a displacement,
>allowing easy access to arrays of ints, etc.
>
>I has occurred to me that this "auto-shifting" might be useful
>for ALL register references. Every reference to a register as
>a source operand would be accompanied by two bits giving a
>shift amount - equivalet to a multiplication by 1, 2, 4, or 8.
.
.stuff deleted.
.
>Anyone want to comment on this idea?
>
>   Radford Neal
>   The University of Calgary

Add with shift instructions can be very nice. They speed address
calculations, and can be used as part of a multiply by small constant.
At least one RISC floating point oriented chip set incorporates such
instructions. (Sorry, they don't like people to talk about their
chipset so I can't say who they are.) However, based on my own coding
practice, it isn't worth giving up two instruction bits for the
capability. Instruction bits are incredibly useful things, and it is
hard enough to stay at 32 bits without 'using just a couple more
bits' for something that isn't going to be used even every tenth
cycle.
-- 
John Danskin				| decwrl!jmd
DEC Workstation Systems Engineering	| (415)853-6724 
100 Hamilton Avenue			| My comments are my own.
Palo Alto, CA  94306			| I do not speak for DEC.