Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!ucsd!telesoft!roger
From: roger@telesoft.UUCP (Roger Arnold @prodigal)
Newsgroups: comp.arch
Subject: Re: conditional branches
Message-ID: <214@telesoft.UUCP>
Date: 23 Feb 88 23:03:11 GMT
References: <191@telesoft.UUCP> <28200099@ccvaxa>
Organization: TeleSoft Inc., San Diego, CA
Lines: 20
Summary: parallel ALU?

In article <28200099@ccvaxa>, aglew@ccvaxa.UUCP writes:
> 
> ..> Compare and branch.
> 
> In case it needs to be restated, special cases of compare and branch
> *DO* *NOT* need to be run through the ALU: x = y, x != y, x < 0, etc.

Grumph!  What's being said here?  It's hard to carry on architectural 
discussions in general terms; everyone (me included) makes unstated
assumptions about the context.  

"x = y" has to be run through SOMEthing.  The values of x and y must 
be accessed, and compared bitwise.  If the point being made is that it
doesn't take a full ALU to do it, well, of course.  All it takes is 
the OR of 32 parallel XOR gates, or something equivalent.  The delay
through such a circuit is less than it is through an adder.  But the
register file accesses are probably going to use the same internal
busses that feed the ALU.  Not that it HAS to be that way, but the
alternatives seem very expensive.  Am I missing something?

- Roger Arnold				..ucsd!telesoft!roger