Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!lll-tis!ames!ucsd!sdcsvax!ucsdhub!hp-sdd!hplabs!sri-unix!quintus!ok
From: ok@quintus.UUCP (Richard A. O'Keefe)
Newsgroups: comp.arch
Subject: Re: Auto-shifted registers
Message-ID: <687@cresswell.quintus.UUCP>
Date: 24 Feb 88 08:15:39 GMT
References: <1370@vaxb.calgary.UUCP> <4307@aw.sei.cmu.edu>
Organization: Quintus Computer Systems, Mountain View, CA
Lines: 19

In article <4307@aw.sei.cmu.edu>, firth@sei.cmu.edu (Robert Firth) writes:
: In article <1370@vaxb.calgary.UUCP: radford@calgary.UUCP (Radford Neal) writes:
: :Several instruction sets, such as the 68020 and the VAX, have
: :an "indexed" addressing mode, in which a register is shifted 
: :left by 0, 1, 2, or 3 bits before being added to a displacement,
: :allowing easy access to arrays of ints, etc.
: Moreover, if you are going to generate slick code for, say, arrays whose
: component size is 12, you have to do all that loop induction, strength
: reduction &c stuff.  Surprise: once you've done that, you can use those
: algorithms for all arrays, junk the scaled-index mode, and get better
: code.
 
It's worth noting that doing the indexing in software is FASTER than
using the scaled modes on the MC68020.  The MC68020 has lots of fancy
addressing modes that the MC68010 has, but (no doubt because they had
to be shoehorned into an existing instruction set) it is usually faster
to forget about them.  (The full-size multiply and divide are quite
another matter!)

I wouldn't like to see auto-increment addressing junked, though.