Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!ll-xn!mit-eddie!bbn!rochester!PT.CS.CMU.EDU!andrew.cmu.edu!zs01+ From: zs01+@andrew.cmu.edu (Zalman Stern) Newsgroups: comp.arch Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC Message-ID: Date: 24 Feb 88 14:40:57 GMT References: <9651@steinmetz.steinmetz.UUCP> Organization: Carnegie Mellon University Lines: 31 In-Reply-To: <9651@steinmetz.steinmetz.UUCP> There are a few things I don't quite get about the RPM-40 info posted here recently. Maybe somebody can clarify these for me. First, in the "DARPA MIPS core ISA", which binding does "MIPS" take? Is this MIPS the corporation, MIPS the Stanford research project, or MIPS the vacuous abbreviation? In some instructions, it appears that the second register argument is only 4 bits long. Does this limit one to the first 16 registers or am I missing something? Can this be extended with a PREFIX instruction even though it isn't an immediate operand? Could you post the ALU opcodes available? Notably do they include multiply an divide? (I know this is probably a stupid question.) How does a coprocessor load work? Does the main processor calculate the address and then tell the coprocessor to pick up the data off the bus when it arrives? Also, how would one send a main processor register to the coprocessor? I don't understand the virtual memory implementation at all. I would appreciate it if someone could elaborate on how this works. I find this a very interesting architecture. My first impression is that the prefix instruction makes the 16 bit instructions reasonable. (A big win in my opinion.) It is rather like having an extra register for holding immediate operands only. I guess it might complicate exception handling though. Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890