Path: utzoo!utgpu!water!watmath!clyde!att-cb!ihnp4!inuxc!iuvax!pur-ee!uiucdcs!uxc.cso.uiuc.edu!ccvaxa!aglew
From: aglew@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <28200110@ccvaxa>
Date: 24 Feb 88 17:23:00 GMT
References: <1642@mips.mips.COM>
Lines: 15
Nf-ID: #R:mips.mips.COM:1642:ccvaxa:28200110:000:760
Nf-From: ccvaxa.UUCP!aglew    Feb 24 11:23:00 1988


>=2.  The instruction set is "DARPA MIPS, core ISA (instruction set
>=    architecture)".  In the GE chip, instructions are 16 bits long.
>=    They are fetched from Instruction Memory two-at-a-time (making
>=32 bit xfrs) at a 20 MHz rate, totalling 40M instructions per sec.
>
>	All the machines listed above are designed so that 'Core ISA' (a
>generic RISC assembly language, designed by Dr Gross of CMU) can be translated
>to their native assembly languages.

Okay, what about this MIPS-like ISA? Will it be assembly language only,
or binary? Will it be possible to run some form of program intermediate
between C and actual assembly through a translator to move between these
families - and will third party software vendors distribute that portable
form?