Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!lll-tis!ames!ll-xn!husc6!ut-sally!im4u!rajiv
From: rajiv@im4u.UUCP (Rajiv N. Patel)
Newsgroups: comp.arch
Subject: 16 & 32 bit vs 32 bit only instructions for RISC.
Message-ID: <2574@im4u.UUCP>
Date: 25 Feb 88 17:05:06 GMT
References: <9651@steinmetz.steinmetz.UUCP> <9678@steinmetz.steinmetz.UUCP>
Reply-To: rajiv@im4u.UUCP (Rajiv N. Patel)
Organization: U. Texas CS Dept., Austin, Texas
Lines: 45
Summary: A Debate.

>
>All you 32-bit instruction advocates : how many of your 32-bits of
>instruction are usually wasted ( like by leading zeroes or ones, or
>unused register specifications ) ? If it sounds like I'd welcome a
>debate on the merits of 16 vs 32 bit instructions : sure. Isn't that
>what comp.arch is for ? And I said a DEBATE, not a fire-fight :-)
>
>--
>	Dennis O'Connor 	oconnor@sunset.steinmetz.UUCP ??
>				ARPA: OCONNORDM@ge-crd.arpa
>    "Nuclear War is NOT the worst thing people can do to this planet."


   	I agree with Dennis, this is a great topic of DEBATE on comp.arch . I
   am not sure if it has already been discussed already but its worth while
   starting again. 
   	In recent years many new(?) RISC architectures have been proposed and
   each of them seems to have a differences in its instruction set.
   Some have only 32 bit instructions whereas others have both 16 and 32
   bit instructions. Then there are some like the Bell CRISP which has
   16, 48 and 80 (believe it or not!) bit instructions. With these variations
   it seems only fair to question how the variable length instruction 
   architectures can compete with the so called fixed length (faster decode)
   architectures.
   	I have done some assembly coding for an on going RISCy project here
   where we have 16 and 32 bit instructions available. In my experience most
   of the programs I have coded (<2K instructions) have about 70-90% of the
   instructions from the 16 bit category. This only tells me that indeed 16
   bit instructions are very useful and the additional amount of time which
   one may incur in decoding 16 and 32 bit instructions could be offset by
   the time saved in fetching instructions from memory/cache assuming a 32
   bits wide bus. The fixed instruction architectures never seem to talk
   about the memory traffic involved for getting all the leading zeros and
   unnecessary third register name. Even CRISP people who had the courage to
   use an 80 bit instruction have 16 bit instructions and claim a very high
   percentage of these.
	I would like to know from other more experienced people (compared to
   me, ofcourse) what could be the different reasons for using a fixed 32 bit
   instruction architecture.


   Rajiv N Patel.
   (rajiv@im4u)
   University of Texas at Austin.