Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!lll-tis!ames!hao!gatech!purdue!i.cc.purdue.edu!j.cc.purdue.edu!pur-ee!uiucdcs!uxc.cso.uiuc.edu!ccvaxa!aglew From: aglew@ccvaxa.UUCP Newsgroups: comp.arch Subject: Re: RPM-40 microprocessor @ 40 MHz; dat Message-ID: <28200112@ccvaxa> Date: 26 Feb 88 16:52:00 GMT References: <1642@mips.mips.COM> Lines: 33 Nf-ID: #R:mips.mips.COM:1642:ccvaxa:28200112:000:1552 Nf-From: ccvaxa.UUCP!aglew Feb 26 10:52:00 1988 ..> Prefix instructions in the GE RPM-40 I like this idea. (I should - I used it in a school project back in '84, before I knew details of the Transputer - I think I got it from an earlier architecture, melded with the 8088's PREFIX instructions.) I particularly like how it begins to let the instruction set get independent of the register size (so long as people do not expect 1<<32 == 0) A question, though: how would you compare PREFIX to an instruction SHIFT and OR -- SHOR r,lit ::== r := (r<<14)|lit? PREFIX always seems to eventually require a specification for one of several literal fields it is extending, plus it requires state to be saved on interrupts, which leans towards assembling the constant in a register. On the other hand, you can always build a decoder that never puts prefix into a register at all, but takes prefix and the prefixed instruction as one packet. This is nice, and makes it a pity to require the register write. What do people (particularly the RPM-40 people) feel on this? Andy "Krazy" Glew. Gould CSD-Urbana. 1101 E. University, Urbana, IL 61801 aglew@gould.com - preferred, if you have nameserver aglew@gswd-vms.gould.com - if you don't aglew@gswd-vms.arpa - if you use DoD hosttable aglew%mycroft@gswd-vms.arpa - domains are supposed to make things easier? My opinions are my own, and are not the opinions of my employer, or any other organisation. I indicate my company only so that the reader may account for any possible bias I may have towards our products.