Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!lll-tis!ames!hao!gatech!purdue!i.cc.purdue.edu!j.cc.purdue.edu!pur-ee!uiucdcs!uxc.cso.uiuc.edu!ccvaxa!aglew
From: aglew@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: 16 & 32 bit vs 32 bit only instruct
Message-ID: <28200113@ccvaxa>
Date: 26 Feb 88 17:02:00 GMT
References: <2574@im4u.UUCP>
Lines: 10
Nf-ID: #R:im4u.UUCP:2574:ccvaxa:28200113:000:537
Nf-From: ccvaxa.UUCP!aglew    Feb 26 11:02:00 1988


The big thing about three address instructions is that
it lets you take maximal advantage of a multiport register
file. Ie. if you *HAVE* to say A=B+C, then A=C;A+=C makes you
pay a penalty. And there is always hope that compilers will
start using the 3 address instructions to avoid dependencies.

But, if you don't use them, why pay for them? Why not have a
decoded instruction cache that takes a compact representation
and generates the canonical form? It doesn't have to be as fancy
as CRISP - Patterson's group had a paper on this.