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From: aglew@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Regi
Message-ID: <28200111@ccvaxa>
Date: 25 Feb 88 20:25:00 GMT
References: <7463@apple.UUCP>
Lines: 20
Nf-ID: #R:apple.UUCP:7463:ccvaxa:28200111:000:656
Nf-From: ccvaxa.UUCP!aglew    Feb 25 14:25:00 1988


..> Condition codes
..> Quick branch conditions: x<0, x=0, etc.

Since this came up, I've been thinking that you can actually divide the
conditions further than Katevenis did:

Real Fast
	x < 0, x >= 0 -- single bit test
Pretty Fast
	x == 0, x != 0, x == y, x != y -- requires unordered test of many bits
Not So Fast
	x < y, etc. -- requires prioritized test of many bits

Pretty fast could be converted into real fast by precomputing OR(all bits)
for each register, eg.; doesn't add state because you don't need to save
it.

(Now if I just could figure out a way to store the overflow CC bit on
a per register basis, without having to store it in memory)