Path: utzoo!utgpu!water!watmath!clyde!att-cb!ihnp4!alberta!calgary!radford
From: radford@calgary.UUCP (Radford Neal)
Newsgroups: comp.arch
Subject: Re: Auto-shifted registers (and ease of compiler writing)
Message-ID: <1390@vaxb.calgary.UUCP>
Date: 25 Feb 88 23:19:24 GMT
References: <1370@vaxb.calgary.UUCP> <4307@aw.sei.cmu.edu>
Organization: U. of Calgary, Calgary, Ab.
Lines: 35

In article <4307@aw.sei.cmu.edu>, firth@sei.cmu.edu (Robert Firth) writes:

> The problem with your suggestion, and with scaled-index modes, is that
> they introduce yet another nonorthogonality into the architecture...

> The Data General Nova did some of what you want, and the Acorn does more.
> Writing a codegenerator for either of them is a pig, because you have to
> handle an unconscionable number of special cases for seemingly simple
> things like multiply, add, subtract, &c.


This brings up an interesting point. What distinguishes an unnecessary
complication in the compiler from an advantagous transfer of work
from run time to compile time?

To my mind, replacing a multiply by two by a shift is an entirely 
appropriate activity for a compiler. I don't really mind doing 
more of the same, if it gives better performance. The added complexity
in the compiler is at the level of detail, not overall design. The
shift is *always* better than the multiply, so there's no real difficulty.

On the other hand, I hate two-address instructions, no matter 
how orthogonal, because they introduce more real options for the
compiler to worry about. The locally optimal code destroys one 
operand. Which operand should you destroy? Should you insteadad save
both operands at the cost of another move? Answering these questions
is a lot more work than handling special cases for multiplication.

As for the auto-shifted registers: my idea is that the shifting is
done at no extra cost, in parellel with the register address decode.
If this isn't true, I'd agree that it is a bad idea. If it is, handling
it in the compiler seems like a small price for doing two operations
in parellel.

   Radford Neal