Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!decwrl!decvax!mcnc!gatech!bloom-beacon!mit-eddie!bbn!rochester!PT.CS.CMU.EDU!andrew.cmu.edu!hs0l+
From: hs0l+@andrew.cmu.edu (Hugh Brinkley Sprunt)
Newsgroups: comp.arch
Subject: Re: Harvard RISC
Message-ID: <oW9oPAy00Uid8840-t@andrew.cmu.edu>
Date: 27 Feb 88 22:29:32 GMT
Organization: Carnegie Mellon University
Lines: 17
In-Reply-To: <4185@lll-winken.llnl.gov>



> I read some "hype" concerning the Motorola RISC chip set
> in Electronics today.  I would like to find a reference
> to the "Harvard RISC" architecture.  Anyone know of
> a suitable paper?

    I think what is being referred to in the Electronics is
    "Harvard" style machines (as opposed to "Princeton"
    style).  A Harvard class machine has separate data
    and instruction buses (or in this case, separate caches
    for instructions and data).  A Princeton class machine
    has only one bus for both instructions and data.

    Does anyone know why and when these classifications
    developed?

				Brink