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From: jesup@pawl18.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: 16 & 32 bit vs 32 bit only instructions for RISC.
Message-ID: <447@imagine.PAWL.RPI.EDU>
Date: 29 Feb 88 11:24:37 GMT
References: <2574@im4u.UUCP> <3508@killer.UUCP>
Sender: news@imagine.PAWL.RPI.EDU
Reply-To: beowulf!lunge!jesup@steinmetz.UUCP
Organization: RPI Public Access Workstation Lab - Troy, NY
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In article <3508@killer.UUCP> elg@killer.UUCP (Eric Green) writes:
>The operative parameter here is, is the bus width {n:n>1) times greater than
>the instruction width? If so, then it doesn't matter how large the
>instructions are -- you'll always be able to fetch multiple instructions
>faster than you can execute them. For example, what you mentioned -- a 32 bit
>bus, with 16 bit instructions. Or a 64 bit bus, with 32 bit instructions.

	Who ever said you had to run the bus a the same speed as the CPU?
The RPM-40 uses fixed-length 16-bit instructions, and fetches 2 every other
cycle.  This has several advantages: cheaper memory, more time for external
caches to respond, and improved efficiency of caches since the same amount of
memory holds twice the number of instructions.

	I do agree that variable length instructions ARE a big drag on
performance in most cases.  There are ways to get some of the effects of
variable length instructions, such as the RPM-40 PREFIX instruction, in a
fixed-length architecture.

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
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(-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)