Path: utzoo!mnetor!uunet!steinmetz!sunset!oconnor
From: oconnor@sunset.steinmetz (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: Condition Codes in General Regi
Message-ID: <9729@steinmetz.steinmetz.UUCP>
Date: 29 Feb 88 19:13:51 GMT
References: <7463@apple.UUCP>
Sender: news@steinmetz.steinmetz.UUCP
Reply-To: sunset!oconnor@steinmetz.UUCP
Organization: GE Corporate R&D Center
Lines: 39

An article by aglew@ccvaxa.UUCP says:
] Since this came up, I've been thinking that you can actually divide the
] conditions further than Katevenis did:
] 
] Real Fast
] 	x < 0, x >= 0 -- single bit test

Yes, and fairly common too. 

] Pretty Fast
] 	x == 0, x != 0, x == y, x != y -- requires unordered test of many bits

Beg to differ. These are not neccessarily pretty fast. More below.

] Not So Fast
] 	x < y, etc. -- requires prioritized test of many bits
]
] Pretty fast could be converted into real fast by precomputing OR(all bits)
] for each register, eg.; doesn't add state because you don't need to save it.

Well, this last trick would help with X == 0 and X != 0, but not the
x==y or x!=y case. But what do you mean by "precompute" ? When
are you going tro do this ? If it's after register fetch, it's
not really "pre-", is it ? 

But about pretty fast : Sorry, not really. It's only a LITTLE bit
faster than "Not so Fast" in CMOS : ever tried to make a 32-input
OR or AND gate go FAST in CMOS ? It's not much faster than the
carry chain, which has order-log2(word-size) gate delays.

] (Now if I just could figure out a way to store the overflow CC bit on
] a per register basis, without having to store it in memory)

Huh ? I missed this, what are you trying to do ?

--
    Dennis O'Connor			      UUNET!steinmetz!sunset!oconnor
		   ARPA: OCONNORDM@ge-crd.arpa
   (-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)