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From: jesup@pawl3.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC
Message-ID: <442@imagine.PAWL.RPI.EDU>
Date: 29 Feb 88 09:29:32 GMT
References: <1642@mips.mips.COM> <409@imagine.PAWL.RPI.EDU> <1666@winchester.mips.COM>
Sender: news@imagine.PAWL.RPI.EDU
Reply-To: beowulf!lunge!jesup@steinmetz.UUCP
Organization: RPI Public Access Workstation Lab - Troy, NY
Lines: 62
Keywords: General Electric, DARPA-MIPS-core-ISA

In article <1666@winchester.mips.COM> mash@winchester.UUCP (John Mashey) writes:
>In article <409@imagine.PAWL.RPI.EDU> beowulf!lunge!jesup@steinmetz.UUCP writes:
>>	Any of those displacements can be prefixed by PFX instruction(s)
>>to extend the displacement up to 32 bits.  Yes, Cond conditionally skips
>>the next instruction, they can be 'stacked' to provide complex conditionals.

>I assume that cond skips the next instruction, including the PFX's??

	Yup.  The COND instruction actually skips the next (non-PFX,non-COND)
instruction.  Essentially, it acts as though PFX is part of the instruction
after it.  Example:

		COND GT,.r1,.r2
		PFX  #$xxx
		COND GE,.r1,#$yy
		PFX  #$qqq
		ADD  .r1,#zz
		MOV  .r2,.r1

If the either cond fails, control goes to the MOV instruction.  Of course,
you would write PFX's in yourself, the assembler does them for you auto-
magicly.

>>	Minor error, there are 21 gp registers, plus a number of special
>>purpose registers, mostly reserved to supervisor mode.  Several are stacks
>>for internal state mapped into register slots.  User available registers
>>are the PC, Trap register, sr2 (has various flags), and the Size register
>>(determines the size of non-word LD/ST, allows some register remapping,
>>and a bit for doing 16-bit overflow detection instead of 32).
>
>How do you address more than 16 gp regs, given the encoding?

	In general, the destination of ALU ops can be any register 0-31.
However, for most ALU ops the source must be in regs 0-15.  There are
two ways around this:
	1)  There are two instructions that reverse the meanings of "source"
	    and "destination".  These are RMOV (reverse move) and RADD (reverse
	    add).  These allow moving the higher registers to the lower
	    or adding them into the lower (two high-freqency ops).
	2)  There is a bit that allows swapping of the regs 8-13 and regs
	    16-21.
Note that loads and stores also must only use regs 0-15.

	There is no guarantee the higher registers will be extremely useful,
but they are very useful for things like temps, or passing args, or
accumulators, etc.  The swap feature can make them much more useful, but
requires more work to use.

>>	VERY rough figures is 1 rpm-40 @ 40Mhz is about equal to 7-9
>>16Mhz 68020's with 0 wait-state memory and no MMU delay.  (Not your standard
>>unix box envirionment 68020.)
>
>I.e., assuming that such 68020s are around 2 vax-mips, this sounds like
>about 14-18 vax-mips, roughly.

	That seems to jibe fairly well.  Of course, only real benchmarks
will tell the story, and those depend on compiler tech quite a bit.

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
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